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Integrated Circuit Systems, Inc.
ICS94228
Programmable System Clock Chip for AMD - K7TM processor
Recommended Application: VIA KT266 style chipset Output Features: * 1 - Differential pair open drain CPU clocks @ 2.7V * 1 - Differential pair push-pull CPU clocks @ 2.5V * 11 - PCI including 1 free running and 1 early @ 3.3V * 1 - 48MHz, @ 3.3V fixed * 1 - 24/48MHz @ 3.3V * 3 - REF @ 3.3V, 14.318MHz. Features: * Programmable output frequency. * Programmable output rise/fall time. * Programmable slew and skew control for CPUCLK, PCICLK, AGP, REF, 48MHz and 24_48MHz. * Real time system reset output. * Spread spectrum for EMI control typically by 7dB to 8dB, with programmable spread percentage. * Watchdog timer technology to reset system if over-clocking causes malfunction. * Uses external 14.318MHz crystal. Skew Specifications: * CPU - CPU: <200ps * PCI - PCI: <500ps * CPU (early - PCI: min=1.0ns, max=2.6ns * CPU cycle to cycle jitter: <250ps
Pin Configuration
VDDREF GND X1 X2 AVDD48 *FS2/48MHz *FS3/24_48MHz GND PCICLK_F *SEL24_48#/PCICLK0 PCICLK1 GND PCICLK2 PCICLK3 VDDPCI PCICLK4 PCICLK5 PCICLK6 GND PCICLK7 PCILCK8 PCICLK9_E VDDPCI SRESET# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 REF0/FS0* REF1/FS1* REF_F REF_STOP#* AGP_STOP#* GND CPUCLKT0 CPUCLKC0 VDDL CPUCLK_CST0 CPUCLK_CSC0 GND CPU_STOP#* PCI_STOP#* PD#* AVDD AGND SDATA SCLK GND AGP2 AGP1 AGP0 VDDAGP
48-Pin 300mil SSOP
* Internal Pull-up Resistor of 120K to VDD
Block Diagram
PLL2 /2 X1 X2 XTAL OSC PLL1 Spread Spectrum
2
Functionality
48MHz (1:0) 24_48MHz
FS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
FS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
FS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
FS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
2
REF (1:0) REF_F
CPU DIVDER
Stop
CPUCLKT0 CPUCLKC0 CPUCLK_CST0 CPUCLK_CSC0 PCICLK9_E
CPU DIVDER
Stop
SEL24_48# SDATA SCLK FS (3:0) PD# PCI_STOP# CPU_STOP# AGP_STOP# REF_STOP#
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Control Logic
PCI DIVDER
Stop
9
PCICLK (8:0) PCICLK_F
AGP DIVDER
Stop
3
AGP (2:0)
Config. Reg. SRESET#
CPU (MHz) 233.33 220.00 210.00 200.00 190.00 180.00 170.00 150.00 140.00 120.00 110.00 66.67 200.00 166.67 100.00 133.33
ICS94228
AG P (MHz) 77.78 73.33 70.00 66.67 76.00 72.00 68.00 75.00 70.00 60.00 66.00 66.67 66.67 66.67 66.67 66.67
PCICLK (MHz) 38.88 36.67 35.00 33.33 38.00 36.00 34.00 37.50 35.00 30.00 33.00 33.33 33.33 33.33 33.33 33.33
ICS94228
Pin Descriptions
PIN NUMBER 1, 15, 23, 25, 2, 8, 12, 19, 29, 37, 43 3 4 5 6 7 9 10 21, 20, 18, 17, 16, 14, 13, 11 22 24 28, 27, 26 30 31 32 33 34 35 36 38 39 40 42 41 44 45 46 47 48 PIN NAME VDD GND X1 X2 AVDD48 FS21, 2 48MHz FS31, 2 24_48MHz PCICLK_F SEL24_48#1, 2 PCICLK0 PCICLK (8:1) PCICLK9_E SRESET#1 AGP (2:0) SCLK SDATA AGND AVDD PD# PCI_STOP# CPU_STOP#
1, 2
TYPE P W R Power supply, nominal 3.3V PWR IN OUT PWR IN OUT IN OUT OUT IN OUT OUT OUT OUT OUT IN I/O PWR PWR IN IN IN OUT OUT PWR OUT OUT IN IN OUT IN OUT IN OUT Ground
DESCRIPTION
Cr ystal input, has inter nal load cap (36pF) and feedback resistor from X2 Cr ystal output, nominally 14.318MHz. Has inter nal load cap (36pF) Power supply, nominal 3.3V Frequency select pin. Latched Input 48MHz output clock, stoppable by REF_Stop Frequency select pin. Latched Input 24 or 48MHz clock output, stoppable by REF_Stop Free running PCI clock not affected by PCI_STOP# for power management. Logic input to select 24 or 48MHz for pin 7 output PCI clock output PCI clock outputs. Early PCI clock. Leads general PCI clocks by 2ns. Can be stopped by PCI_STOP#. Real time system reset signal for watchdog tmer timeout. This signal is active low. AGP clock outputs Clock input of I2C input, 5V tolerant input Data pin for I2C circuitry 5V tolerant Analog ground Power supply, nominal 3.3V Asynchronous active low input pin used to power down the device into a low power state. The inter nal clocks are disabled and the VCO and the cr ystal are s t o p p e d . T h e l a t e n c y o f t h e p ow e r d ow n w i l l n o t b e g r e a t e r t h a n 3 m s. Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level, when input low This asynchronous input halts CPUCLKT, CPUCLKC & CUCLKC_CS clocks at logic "0" level when driven low. "Complementary" clock of differential pair output chipset (push-pull). "True" clock of differential pair CPU output chipset (push-pull). Power supply for CPUCLKs, nominal 2.5V "True" clock of differential pair CPU output. These open drain outputs need an external 1.5V pull-up (open drain). "Complementary" clock of differential pair CPU output. These open drain outputs need an external 1.5V pull-up (open drain). Stops all AGP clocks at logic 0 level, when input low Stops REF, 48MHz and 24/48MHz clocks at logic 0 level, when input low. 14.318 MHz free running reference clock., not afftected by REF_STOP# Frequency select pin. Latched Input 14.318 MHz reference clock. Frequency select pin. Latched Input 14.318 MHz reference clock.
CPUCLK_CSC0 CPUCLK_CST0 VDDL CPUCLKT0 CPUCLKC0 AGP_STOP# REF_STOP# REF_F FS11, 2 REF1 FS01, 2 REF0
Notes: 1: Internal Pull-up Resistor of 120K to 3.3V on indicated inputs 2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor to program logic Hi to VDD or GND for logic low.
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ICS94228
General Description
The ICS94228 is a main clock synthesizer chip for AMD-K7 based systems with VIA style chipset. This provides all clocks required for such a system. The ICS94228 belongs to ICS new generation of programmable system clock generators. It employs serial programming I2C interface as a vehicle for changing output functions, changing output frequency, configuring output strength, configuring output to output skew, changing spread spectrum amount, changing group divider ratio and dis/ enabling individual clocks. This device also has ICS propriety 'Watchdog Timer' technology which will reset the frequency to a safe setting if the system become unstable from over clocking.
SRESET# Signal Description
The SRESET# signal from ICS94228 system clock generator is a real time active low pulse that can be used to reset the system. The Open-Drain Nch output Reset# pin needs to be tied to the system reset line which has a pull-up resistor. When activated, the SRESET# output will be driven to a low with a 32ms pulse width.
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ICS94228
General I2C serial interface information for the ICS94228 How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending Byte 0 through Byte 16 (see Note 2) * ICS clock will acknowledge each byte one at a time * Controller (host) sends a Stop bit * * * * * * * *
How to Read:
* * * * * * * Controller (host) will send start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends Byte 0 through byte 6 (default) ICS clock sends Byte 0 through byte X (if X(H) was written to byte 6). * Controller (host) will need to acknowledge each byte * Controller (host) will send a stop bit
How to Write:
Controller (Host) Start Bit Address D2(H) Dummy Command Code ICS (Slave/Receiver)
How to Read:
Controller (Host) Start Bit Address D3(H) ICS (Slave/Receiver)
ACK ACK
Dummy Byte Count
ACK Byte Count
ACK
Byte 0
ACK
ACK
Byte 0
Byte 1
ACK
ACK
Byte 1
Byte 2
ACK
ACK
Byte 2
Byte 3
ACK
ACK
Byte 3
Byte 4
ACK
ACK
Byte 4
Byte 5
ACK
ACK
Byte 5
Byte 6
ACK
ACK If 7H has been written to B6 ACK
Byte 6
Byte 7
ACK
Byte 14
ACK
Byte 15
ACK
Byte 16
ACK
Stop Bit
If 1AH has been written to B6 ACK If 1BH has been written to B6 ACK If 1CH has been written to B6 ACK Stop Bit
Byte 14 Byte 15 Byte 16
*See notes on the following page.
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ICS94228
Brief I2C registers description for ICS94228 Programmable System Frequency Generator
Register Name Functionality & Frequency Select Register Output Control Registers Byte 0 Description Output frequency, hardware / I2C frequency select, spread spectrum & output enable control register. Active / inactive output control registers/latch inputs read back. Byte 11 bit[7:4] is ICS vendor id 1001. Other bits in this register designate device revision ID of this part. Writing to this register will configure byte count and how many byte will be read back. Do not write 00 H to this byte. Writing to this register will configure the number of seconds for the watchdog timer to reset. Watchdog enable, watchdog status and programmable 'safe' frequency' can be configured in this register. This bit select whether the output frequency is control by hardware/byte 0 configurations or byte 11&12 programming. These registers control the dividers ratio into the phase detector and thus control the VCO output frequency. These registers control the spread percentage amount. Increment or decrement the group skew amount as compared to the initial skew. These registers will control the output rise and fall time. PWD Default See individual byte description See individual byte description See individual byte description
1, 2, 3
Vendor ID & Revision ID Registers
5, 6, 7
Byte Count Read Back Register Watchdog Enable Register Watchdog Control Registers
8
08H
4
10H
000,0000
VCO Control Selection Bit
4, 5
0
VCO Frequency Control Registers
9, 10
Depended on hardware/byte 0 configuration Depended on hardware/byte 0 configuration See individual byte description See individual byte description
Spread Spectrum Control Registers Group Skews Control Registers Output Rise/Fall Time Select Registers
11, 12
13, 14
15, 16
Notes:
1. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Readback will support standard SMBUS controller protocol. The number of bytes to readback is defined by writing to byte 8. When writing to byte 11 - 12, and byte 13 - 14, they must be written as a set. If for example, only byte 14 is written but not 15, neither byte 14 or 15 will load into the receiver. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only Block-Writes from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition, as shown.
2. 3. 4. 5. 6.
7.
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ICS94228
Serial Configuration Command Bitmap
Byte0: Functionality and Frequency Select Register (default = 0)
Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 CPUCLK AGPCLK PCICLK SSB1 SSB0 FS3 FS2 FS1 FS0 0 0 0 0 0 0 233.33 77.78 38.88 0 0 0 0 0 1 220.00 73.33 36.67 0 0 0 0 1 0 210.00 70.00 35.00 0 0 0 0 1 1 200.00 66.67 33.33 0 0 0 1 0 0 190.00 76.00 38.00 0 0 0 1 0 1 180.00 72.00 36.00 0 0 0 1 1 0 170.00 68.00 34.00 0 0 0 1 1 1 150.00 75.00 37.50 0 0 1 0 0 0 140.00 70.00 35.00 0 0 1 0 0 1 120.00 60.00 30.00 0 0 1 0 1 0 110.00 66.00 33.00 0 0 1 0 1 1 66.67 66.67 33.33 0 0 1 1 0 0 200.00 66.67 33.33 0 0 1 1 0 1 166.67 66.67 33.33 0 0 1 1 1 0 100.00 66.67 33.33 0 0 1 1 1 1 133.33 66.67 33.33 0 1 0 0 0 0 200.00 66.67 33.33 0 1 0 0 0 1 166.67 66.67 33.33 0 1 0 0 1 0 100.00 66.67 33.33 0 1 0 0 1 1 133.33 66.67 33.33 1 0 0 1 0 0 200.00 66.67 33.33 1 0 0 1 0 1 166.67 66.67 33.33 1 0 0 1 1 0 100.00 66.67 33.33 1 0 0 1 1 1 133.33 66.67 33.33 1 1 1 0 0 0 200.00 66.67 33.33 1 1 1 0 0 1 166.67 66.67 33.33 1 1 1 0 1 0 100.00 66.67 33.33 1 1 1 0 1 1 133.33 66.67 33.33 1 0 1 1 0 0 200.00 66.67 33.33 1 0 1 1 0 1 166.67 66.67 33.33 1 0 1 1 1 0 100.00 66.67 33.33 1 0 1 1 1 1 133.33 66.67 33.33 Bit 6: 0 = Hardware select; 1 = I2C select. Default is OFF. Bit 7: 0 = Spread off; 1 = Spread spectrum enable. Default is OFF
Spread Percentage +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread 0 to -0.5% Down Spread 0 to -0.5% Down Spread 0 to -0.5% Down Spread 0 to -0.5% Down Spread +/- 0.50% Center Spread +/- 0.50% Center Spread +/- 0.50% Center Spread +/- 0.50% Center Spread +/- 0.75% Center Spread +/- 0.75% Center Spread +/- 0.75% Center Spread +/- 0.75% Center Spread 0 to +0.5% Up Spread 0 to +0.5% Up Spread 0 to +0.5% Up Spread 0 to +0.5% Up Spread
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ICS94228
Byte 1: CPU, Active/Inactive Register (1= enable, 0 = disable)
Byte 2: PCI, Active/Inactive Register (1= enable, 0 = disable)
BIT
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN#
42, 41 39, 38 6 7 28 27 26
PWD
1 1 1 1 1 1 1 1
DESCRIPTION
CPUCLKT0, CPUCLKC0 CPUCLK_CST0, CPUCLK_CSC0 48MHz 24_48MHz FS0 (readback) AGP2 AGP1 AGP0
BIT
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN#
20 18 17 16 14 13 11 10
PWD
1 1 1 1 1 1 1 1
DESCRIPTION
PCICLK7 PCICLK6 PCICLK5 PCICLK4 PCICLK3 PCICLK2 PCICLK1 PCICLK0
Byte 3: PCI, REF, Active/Inactive Register (1= enable, 0 = disable)
Byte 4: Watch Dog Register (1= enable, 0 = disable)
BIT
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN#
9 22 21 46 47 48
PWD
1 1 1 1 1 1 1 1
DESCRIPTION
PCICLK_F PCICLK9_E FS1 (readback) PCICLK8 REF_F FS2 (readback) REF1 REF0
BIT
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN# PWD
0 0 0 0 1 0 0 0
DESCRIPTION
Watch dog enable 0: stop 1: start M/N program enable
The decimal representation of these 8 bits correspond to 290ms or 1ms the watchdog timer will wait before it goes to alarm mode and reset the frequency to the safe setting. Default at power up is 8X 580ms = 4.6 seconds.
Byte 5: Vendor Specific Feature, Active/Inactive Register (1= enable, 0 = disable)
BIT
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN# PWD
0 0 0 1 1 1 1 1
DESCRIPTION
SEL24_48# (readback) FS3 (readback) Watchdog status: 0=Normal 1=Alarm SSB1 FS3 FS2 FS1 FS0
Byte 6: Vendor ID1 , Active/Inactive Register (1= enable, 0 = disable)
BIT Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
PIN# -
PWD DESCRIPTION 0 0 Device ID 0 1 0 0 Vendor ID 0 1
Notes:
1. Inactive means outputs are held LOW and are disabled from switching.
Note: Don't write into this register, writing into this register can cause malfunction
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ICS94228
Byte 7: Vendor ID2, Active/Inactive Register (1= enable, 0 = disable)
Byte 8: Byte Count Register (1= enable, 0 = disable)
BIT
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN#
-
PWD
0 0 0 0 1 1 0 0
DESCRIPTION
Revision ID Revision ID Revision ID Revision ID Revision ID Revision ID Revision ID Revision ID
BIT
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN#
-
PWD
0 0 0 0 1 0 0 0
DESCRIPTION
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Byte 9: VCO Frequency Control Register (1= enable, 0 = disable)
Byte 10: VCO Frequency Control Register (1= enable, 0 = disable)
BIT
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN#
-
PWD
X X X X X X X X
DESCRIPTION
VCO Divder Bit 0 REF Divder Bit 6 REF Divder Bit 5 REF Divder Bit 4 REF Divder Bit 3 REF Divder Bit 2 REF Divder Bit 1 REF Divder Bit 0
BIT
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN#
-
PWD
X X X X X X X X
DESCRIPTION
VCO Divider Bit 8 VCO Divider Bit 7 VCO Divider Bit 6 VCO Divider Bit 5 VCO Divider Bit 4 VCO Divider Bit 3 VCO Divider Bit 2 VCO Divider Bit 1
Byte 11: VCO Spread Spectrum Control Register (1= enable, 0 = disable)
Byte 12: VCO Spread Spectrum Control Register (1= enable, 0 = disable)
BIT
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN#
-
PWD
X X X X X X X X
DESCRIPTION
Spread Spectrum Bit 7 Spread Spectrum Bit 6 Spread Spectrum Bit 5 Spread Spectrum Bit 4 Spread Spectrum Bit 3 Spread Spectrum Bit 2 Spread Spectrum Bit 1 Spread Spectrum Bit 0
BIT
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN#
-
PWD
X X X X X X X X
DESCRIPTION
Reserved Reserved Reserved Spread Spectrum Bit 12 Spread Spectrum Bit 11 Spread Spectrum Bit 10 Spread Spectrum Bit 9 Spread Spectrum Bit 8
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ICS94228
Byte 13: Output Skew Control Register (1= enable, 0 = disable)
Byte 14: Output Skew Control Register (1= enable, 0 = disable)
BIT
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN#
-
PWD
0 0 0 0 0 0 0 0
DESCRIPTION
BIT
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN#
-
PWD
0 0 1 0 0 0 0 0
DESCRIPTION
CPUCLKC0/T0 Skew Control
PCICLK(8:0) Skew Control
AGP(2:0) Skew Control PCICLK9_E: Slew Rate Control
CPUCLKC_CST/C Skew Control
Byte 15: Output Rise/Fall Time Select Register (1= enable, 0 = disable)
Byte 16: Output Rise/Fall Time Select Register (1= enable, 0 = disable)
BIT
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN#
-
PWD
0 0 0 0 1 0 0 0
DESCRIPTION
CPUCLKT0 CPUCLKC0 CPUCLKT_CST CPUCLKC_CSC AGP(2:0): Slew Rate Control REF(2:0): Slew Rate Control
BIT
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN#
-
PWD
0 0 1 0 0 0 0 0
DESCRIPTION
PCICLK(3:0): Slew Rate Control PCICLK(8:4): Slew Rate Control 48MHz: Slew Rate Control 24_48MHz: Slew Rate Control
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ICS94228
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.5 V to VDD +0.5 V Ambient Operating Temperature . . . . . . . . . . 0C to +70C Storage Temperature . . . . . . . . . . . . . . . . . . . . -65C to +150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5% (unless otherwise stated) PARAMETER Input High Voltage Input Low Voltage Input High Current Input Low Current Input Low Current Operating Supply Current Power Down Input frequency Input Capacitance1 Clk Stabilization1 Skew Window
1
SYMBOL VIH VIL I IH IIL1 IIL2 I DD3.3OP66
CONDITIONS
MIN 2 VSS - 0.3 -5 -200
TYP
VIN = VDD VIN = 0 V; Inputs with no pull-up resistors VIN = 0 V; Inputs with pull-up resistors CL = 0 pF; Select @ 66MHz
MAX UNITS VDD + 0.3 V 0.8 V 5 mA mA mA 180 600 mA mA MHz pF pF ms ns ps
IDD3.3OP100 CL = 0 pF; Select @ 100MHz IDD3.3OP133 CL = 0 pF; Select @ 133MHz PD Fi CIN CINX TSTAB t CPU-PCI tCPU-AGP VDD = 3.3 V; Logic Inputs X1 & X2 pins From VDD = 3.3 V to 1% target Freq. 2.3 300 12 27 14.318
16 5 45 3 2.6 550
Guaranteed by design, not 100% tested in production.
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ICS94228
Electrical Characteristics - REF
TA = 0 - 70C; V DD = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time1 Fall Time1 Duty Cycle1
1
SYMBOL V OH5 V OL5 I OH5 IOL5 t r5 t f5 dt5
CONDITIONS IOH = -12 mA IOL = 9 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, V OH = 2.4 V VOH = 2.4 V, V OL = 0.4 V VT = 1.5V
MIN 2.4
TYP
16 1.3 1.4 45 54
MAX UNITS V 0.4 V -22 mA mA 4 4 57 ns ns %
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - CPUCLK (Open Drain)
TA = 0 - 70C; VDD = 3.3 V +/-5%; VDDL=2.5V+/-5%; CL = 20 pF (unless otherwise stated) PARAMETER Output Impedance Output High Voltage Output Low Voltage Output Low Current Rise Time1, CPUCLK Fall Time , CPUCLK Differential voltage-AC1 Differential voltage-DC1 Differential Crossover Voltage1 CPUCLK(Open Drain) Duty Cycle1 Skew
1 1 1
SYMBOL ZO V OH2B V OL2B IOL2B t r2B t f2B V DIF V DIF VX dt2B tsk2B
CONDITIONS VO = V X Termination to Vpull-up(external) Termination to Vpull-up(external) VOL = 0.3V V OL = 20%, V OH = 80% VOH = 80%, V OL=20% Note 2 Note 2 Note 3 V T = 50% V T = 50%
MIN
TYP
MAX
1
1.2 0.4
UNITS W V V mA
18 2.2 1.3 0.4 0.2 1.2 45 1.4 50 140 2.5 2.0 Vpullup(external) + 0.6 Vpullup(external) + 0.6 1.7 55 200
ns ns V V V %
Jitter, Cycle-to-cycle , V T = VX tjcyc-cyc2B 250 150 ps CPUCLK Notes: 1 - Guaranteed by design, not 100% tested in production. 2 - VDIF specifies the minimum input differential voltages (VTR-VCP) required for switching, where VTR is the "tr 3 - Vpullup(external) = 2.7V, Min = Vpullup(external)/2-150mV; Max=(Vpullup(external)/2)+150mV
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ICS94228
Electrical Characteristics - PCICLK
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 30 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time1 Fall Time1 Duty Cycle1 Jitter Cycle-to-Cycle Skew1(window)
1 1
SYMBOL VOH1 VOL1 IOH1 IOL1 tr1 tf1 dt1 tjcyc-cyc1 Tsk1
CONDITIONS IOH = -11 mA IOL = 9.4 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4V VOH = 2.4V, VOL = 0.4V VT = 1.5 V VT = 1.5V VT = 1.5V
MIN 2.6
TYP
MAX 0.4 -16
19 2.0 1.8 45 51 130 330 2.5 2.5 55 500 500
UNITS V V mA mA ns ns % ps ps
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - PCICLK_E
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time1 Fall Time
1 1 1
SYMBOL V OH1 VOL1 IOH1 IOL1 tr1 tf1 dt1 tjcyc-cyc1 Tsk1
CONDITIONS I OH = -11 mA I OL = 9.4 mA V OH = 2.0 V V OL = 0.8 V V OL = 0.4 V, V OH = 2.4V V OH = 2.4V, VOL = 0.4V V T = 1.5 V V T = 1.5V V T = 1.5V
MIN 2.6
TYP
MAX 0.4 -12
12 1.7 2.0 45 52 100 2.3 2.5 2.5 55 500 2.7
UNITS V V mA mA ns ns % ps ns
Duty Cycle
Jitter Cycle-to-Cycle
1
PCI_E to PCI Skew1
Guaranteed by design, not 100% tested in production.
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ICS94228
Electrical Characteristics - 24MHz, 48MHz
TA = 0 - 70C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time1 Fall Time
1 1 1
SYMBOL V OH5 V OL5 IOH5 I OL5 tr5 tf 5 dt 5 tjabs5
CONDITIONS I OH = -16 mA I OL = 9 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4V VOH = 2.4 V, VOL = 0.4V VT = 1.5 V VT = 1.5 V
MIN 2.4
TYP
MAX 0.4 -22
16 1.3 1.3 45 -1 52 190 4 4 55 500 1
UNITS V V mA mA ns ns % ps ns
Duty Cycle
Jitter, Cycle-to-Cycle Jitter, Absolute1
1
tjcyc-cyc1 VT = 1.5 V
Guaranteed by design, not 100% tested in production.
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ICS94228
Shared Pin Operation Input/Output Pins
The I/O pins designated by (input/output) on the ICS94228 serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. At the end of PowerOn reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm (10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Figure 1 shows a means of implementing this function when a switch or 2 pin header is used. With no jumper is installed the pin will be pulled high. With the jumper in place the pin will be pulled low. If programmability is not necessary, than only a single resistor is necessary. The programming resistors should be located close to the series termination resistor to minimize the current loop area. It is more important to locate the series termination resistor close to the driver than the programming resistor.
Programming Header Via to Gnd Device Pad 2K W
Via to VDD
8.2K W Clock trace to load Series Term. Res.
Fig. 1
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ICS94228
AGP_STOP# Timing Diagram
AGP_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the AGP clocks. for low power operation. AGP_STOP# is synchronized by the ICS94228. The AGPCLKs will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse. AGPCLK on latency is less than AGPCLK and AGPCLK off latency is less than 3 AGPCLKs. This function is available only with MODE pin latched low.
Notes: 1. All timing is referenced to the internal CPUCLK. 2. AGP_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized to the CPUCLKs inside the ICS4228. 3. All other clocks continue to run undisturbed. 4. PD# and PCI_STOP# are shown in a high (true) state.
5. Only applies if MODE pin latched 0 at power up.
CPU_STOP# Timing Diagram
CPU_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPUCLKs for low power operation. CPU_STOP# is synchronized by the ICS94228. All other clocks will continue to run while the CPUCLKs clocks are disabled. The CPUCLKs will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPUCLK on latency is less than 4 CPUCLKs and CPUCLK off latency is less than 4 CPUCLKs.
INTERNAL CPUCLK PCICLK CPU_STOP# PD# (High) CPUCLKT CPUCLKT_CST CPUCLKC CPUCLKC_CSC
Notes: 1. All timing is referenced to the internal CPUCLK. 2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized to the CPUCLKs inside the ICS94228. 3. All other clocks continue to run undisturbed. 4. PD# and PCI_STOP# are shown in a high (true) state.
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ICS94228
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering down the clock synthesizer. Internal clocks are not running after the device is put in power down. When PD# is active low all clocks need to be driven to a low value and held prior to turning off the VCOs and crystal. The power up latency needs to be less than 3 mS. The power down latency should be as short as possible but conforming to the sequence requirements shown below. PCI_STOP# and CPU_STOP# are considered to be don't cares during the power down operations. The REF and 48MHz clocks are expected to be stopped in the LOW state as soon as possible. Due to the state of the internal logic, stopping and holding the REF clock outputs in the LOW state may require more than one clock cycle to complete.
PD#
CPUCLKT CPUCLKC
PCICLK VCO Crystal
Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS94228 device). 2. As shown, the outputs Stop Low on the next falling edge after PD# goes low. 3. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside this part. 4. The shaded sections on the VCO and the Crystal signals indicate an active clock. 5. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz.
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS94228. It is used to turn off the PCICLK clocks for low power operation. PCI_STOP# is synchronized by the ICS94228 internally. The minimum that the PCICLK clocks are enabled (PCI_STOP# high pulse) is at least 10 PCICLK clocks. PCICLK clocks are stopped in a low state and started with a full high pulse width guaranteed. PCICLK clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK clock.
CPUCLK (Internal)
PCICLK_F (Internal) PCICLK_F (Free-running) CPU_STOP#
PCI_STOP#
PCICLK
Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS94228 device.) 2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized inside the ICS94228. 3. All other clocks continue to run undisturbed. 4. CPU_STOP# is shown in a high (true) state.
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ICS94228
N
c
SYMBOL
L
INDEX AREA
E1
E
12 D h x 45
a
A A1
A A1 b c D E E1 e h L N
In Millimeters COMMON DIMENSIONS MIN MAX 2.41 2.80 0.20 0.40 0.20 0.34 0.13 0.25 SEE VARIATIONS 10.03 10.68 7.40 7.60 0.635 BASIC 0.38 0.64 0.50 1.02 SEE VARIATIONS 0 8 VARIATIONS D mm. MIN MAX 15.75 16.00
In Inches COMMON DIMENSIONS MIN MAX .095 .110 .008 .016 .008 .0135 .005 .010 SEE VARIATIONS .395 .420 .291 .299 0.025 BASIC .015 .025 .020 .040 SEE VARIATIONS 0 8
-Ce
b SEATING PLANE .10 (.004) C
N 48
10-0034
D (inch) MIN .620 MAX .630
Reference Doc.: JEDEC Publication 95, MO-118
300 mil SSOP Package
Ordering Information
ICS94228yFLF-T
Example:
ICS XXXX y F LF- T
Designation for tape and reel packaging Lead Free (Optional) Package Type F = SSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device
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